Semiconductor chips with reduced stress from underfill at edge of chip

ABSTRACT

Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes a first dielectric layer on top of the N interconnect layers, and a second dielectric layer on top of the first dielectric layer. The second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers. The chip further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. The chip further includes a laminate substrate on top of the underfill layer. The underfill layer is sandwiched between the second dielectric layer and the laminate substrate.

This application is a divisional application claiming priority to Ser. No. 11/830,228, filed Jul. 30, 2007.

FIELD OF THE INVENTION

The present invention relates to semiconductor chips, and more specifically, to semiconductor chips in which underfill layers are not likely to create splits.

BACKGROUND OF THE INVENTION

In a conventional semiconductor chip, underfill layers that fill the space between the laminate substrate and the semiconductor chip, can create splits in the chip. Therefore, there is a need for a structure (and method of forming the same), in which underfill layers are not likely to create splits in the semiconductor chip.

SUMMARY OF THE INVENTION

The present invention provides a semiconductor chip, comprising (a) a semiconductor substrate; (b) a transistor on the semiconductor substrate; (c) N interconnect layers on top of the semiconductor substrate and the transistor, wherein N is a positive integer, and wherein the transistor is electrically coupled to the N interconnect layers; (d) a first dielectric layer on top of the N interconnect layers; (e) a second dielectric layer on top of the first dielectric layer, wherein the second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers; (f) an underfill layer on top of the second dielectric layer, wherein the second dielectric layer is sandwiched between the first dielectric layer and the underfill layer; and (g) a laminate substrate on top of the underfill layer, wherein the underfill layer is sandwiched between the second dielectric layer and the laminate substrate.

The present invention provides a structure (and method of forming the same), in which underfill layers are not likely to create splits in the semiconductor chip.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1N (cross-section views) illustrate a fabrication process for forming a semiconductor chip, in accordance with embodiments of the present invention.

FIGS. 2A-2D (cross-section views) illustrate a fabrication process for forming a semiconductor chip, in accordance with embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1A-1N (cross-section views) illustrate a fabrication process for forming a semiconductor chip 100, in accordance with embodiments of the present invention. More specifically, with reference to FIG. 1A, the fabrication of the semiconductor structure 100 starts with a semiconductor (silicon, germanium, etc.) substrate 110.

Next, in one embodiment, transistors (only a source/drain region 111 of one of the transistors is shown for simplicity) and a STI (Shallow Trench Isolation) region 112 are formed on the semiconductor substrate 110 by using conventional methods. The STI region 112 comprises a dielectric material such as silicon dioxide.

Next, with reference to FIG. 1B, in one embodiment, a BPSG (Boro-Phospho-Silicate Glass) layer 113 is formed on top of the entire structure 100 of FIG. 1A. The BPSG layer 113 can be formed by CVD (Chemical Vapor Deposition) of BPSG material on top of the entire structure 100 of FIG. 1A, followed by a CMP (Chemical Mechanical Polishing) step.

Next, in one embodiment, contact regions 114 a, 114 b, 114 c, and 114 d are formed in the BPSG layer 113 by using a conventional method. The contact region 114 a is electrically coupled to the source/drain region 111, whereas the contact regions 114 b, 114 c, and 114 d are in direct physical contact with the STI region 112. The contact regions 114 a, 114 b, 114 c, and 114 d can comprise tungsten. There is a thin metal (e.g., Titanium (Ti)) liner layer (not shown) on side walls and a bottom wall of the contact region 114 a.

Next, with reference to FIG. 1C, in one embodiment, an interconnect layer 120 is formed on top of the structure 100 of FIG. 1B by using a conventional method. The interconnect layer 120 includes (i) a dielectric layer 121, and (ii) metal lines 122 a, 122 b, and 122 c in the dielectric layer 121. The metal line 122 a is electrically coupled to the contact region 114 a, whereas the metal lines 122 b, 122 c are in direct physical contact with the contact regions 114 b and 114 c and the contact region 114 d, respectively. The metal lines 122 a, 122 b, and 122 c can comprise copper. In an alternative embodiment, there are thin metal (e.g., tantalum nitride) liner layers (not shown) on side walls and bottom walls of the metal lines 122 a, 122 b, and 122 c.

Next, with reference to FIG. 1D, in one embodiment, a nitride layer 123 is formed on top of the structure 100 of FIG. 1C. The nitride layer 123 can be formed by CVD of silicon nitride on top of the interconnect layer 120.

Next, with reference to FIG. 1E, in one embodiment, an interconnect layer 130 is formed on top of the nitride layer 123 by using a conventional method. The interconnect layer 130 includes (i) a dielectric layer 131 on top of the nitride layer 123, (ii) metal vias 132 a, 132 b, 132 c, and 132 d embedded in the dielectric layer 131, and (iii) metal lines 133 a, 133 b, and 133 c electrically coupled to the metal via 132 a, the metal vias 132 b and 132 c, and the metal via 132 d, respectively. The metal via 132 a is electrically coupled to the metal line 122 a, whereas the metal vias 132 b and 132 c and the metal via 132 d are in direct physical contact with the metal lines 122 b and 122 c, respectively. The metal vias 132 a, 132 b, 132 c, and 132 d and metal lines 133 a, 133 b, and 133 c can comprise copper. In an alternative embodiment, there are thin metal (e.g., tantalum nitride) liner layers (not shown) on side walls and bottom walls of the metal vias 132 a, 132 b, 132 c, and 132 d and metal lines 133 a, 133 b, and 133 c.

Next, with reference to FIG. 1F, in one embodiment, a dielectric layer 140 (comprising nitride in one embodiment) is formed on top of the structure 100 of FIG. 1E. The nitride layer 140 can be formed by CVD of silicon nitride on top of the interconnect layer 130. The structure 100 comprises a chip region 117 and a dicing channel region 118, which are separated by a dashed line as shown in FIG. 1F.

Next, in one embodiment, the structure 100 is diced (by a laser beam (not shown) in one embodiment) at the dicing channel region 118 until a portion of the semiconductor substrate 110 is removed, resulting in a dicing trench 116 (FIG. 1G).

Next, with reference to FIG. 1H, in one embodiment, a hole 142 a and trenches 142 b and 142 c are created in the nitride layer 140 by etching the nitride layer 140 until top surfaces 134 a, 134 b, and 134 c of the metal lines 133 a, 133 b, and 133 c, respectively, are exposed to the surrounding ambient. The step of etching the nitride layer 140 to form the hole 142 a and trenches 142 b and 142 c can involve photo-lithography and then dry etching.

Next, with reference to FIG. 1I, in one embodiment, pads 150 a, 150 b, and 150 c (comprising aluminum (Al) in one embodiment) are formed on top of the structure 100 of FIG. 1H such that (i) the Al pads 150 a, 150 b, and 150 c fill the hole 142 a and trenches 142 b and 142 c, respectively, and (ii) the Al pad 150 a is electrically coupled to the metal line 133 a. The Al pads 150 a, 150 b, and 150 c can be formed by (a) forming a conformal Al layer (not shown) on the entire structure 100 of FIG. 1H including in the hole 142 a and trenches 142 b and 142 c and on side walls and bottom wall of the dicing trench 116, and then (b) directionally and selectively etching back the Al layer stopping at the nitride layer 140. The directional and selective etching in step (b) may be performed using traditional lithographic and etching processes such that what remains of the Al layer after the etching are the Al pads 150 a, 150 b, and 150 c.

In one embodiment, the side wall of the dicing trench 116 is slanted (85-89 degrees), and the etching of the Al layer in step (b) above has a small isotropic component (10-50 nm). As a result, the etching of the Al layer in step (b) above can completely remove Al from the side walls and bottom wall of the dicing trench 116.

The Al pad 150 b, the metal lines 133 b and 122 b, the vias 132 b and 132 c, and the contact regions 114 b and 114 c can be collectively referred to as an edge seal region 114 b+ 114 c+ 122 b+ 132 b+ 132 c+ 133 b+ 150 b. The Al pad 150 c, the metal lines 133 c and 122 c, the via 132 c, and the contact region 114 d can be collectively referred to as a split stop region 114 d+ 122 c+ 132 d+ 133 c+ 150 c. The edge seal region 114 b+ 114 c+122 b+132 b+132 c+133 b+150 b and the split stop region 114 d+122 c+132 d+133 c+150 c each form a closed loop on a perimeter of the semiconductor chip 100 and prevent splits from propagating from the edge of semiconductor chip 100 into the center of semiconductor chip 100.

Next, with reference to FIG. 1J, in one embodiment, a photosensitive polyimide (PSPI) layer 160 is formed on top of the entire structure 100 of FIG. 1I. More specifically, the PSPI layer 160 is formed by spin-applying a solvent-soluble polyimide on the entire structure 100 of FIG. 1I including in the dicing trench 116.

Next, in one embodiment, a hole 161 is created in the PSPI layer 160 such that a top surface 151 of the Al pad 150 a is exposed to the surrounding ambient via the hole 161. More specifically, the hole 161 is formed in the PSPI layer 160 by using a conventional lithographic process. It should be noted that polyimide is a photosensitive polymer. After forming the hole 161, the PSPI layer 160 is cured at a high temperature (between 150 C and 400 C) to remove the solvent and to cross-link the polymer.

Next, with reference to FIG. 1K, in one embodiment, a bump limiting metallurgy (BLM) region 170 and a solder bump 171 are formed in the hole 161 and on top of the Al pad 150 a by using a conventional method. The solder bump 171 and the BLM region 170 are electrically coupled to the Al pad 150 a. The BLM region 170 can comprise multiple layers of titanium-tungsten (TiW), copper (Cu), chrome (Cr), and gold (Au), whereas the solder bump 171 can comprise a mixture of silver (Ag) and tin (Sn).

Next, in one embodiment, a chip dicing process is performed wherein a blade (not shown) can be used to cut through the dicing channel region 118, resulting in the separated semiconductor chip 100 in FIG. 1L. It is should be noted that the PSPI layer 160 is still on a side wall 115.

Next, with reference to FIG. 1M, in one embodiment, the chip 100 (in FIG. 1L) is aligned to a laminate substrate 180. Then, the solder bump 171 is bonded directly to a pad 181 of the laminate substrate 180 at a high temperature (above the melting point of the solder) and then cooled down.

Next, in one embodiment, space 182 between the PSPI layer 160 and the laminate substrate 180 is filled with an underfill material (e.g., epoxy with silicon dioxide filler) resulting in an underfill layer 190 in FIG. 1N.

It should be noted that the material of the PSPI layer 160 (polyimide) is flexible, therefore, splits are not likely to occur at the side wall 115 (the interfacing surface between the PSPI layer 160 and the interconnect layers 120 and 130 in FIG. 1N).

FIGS. 2A-2D (cross-section views) illustrate a fabrication process for forming a semiconductor chip 200, in accordance with embodiments of the present invention. More specifically, the fabrication process starts out with the structure 200 of FIG. 2A. In one embodiment, the structure 200 of FIG. 2A is similar to the structure 100 of FIG. 1E. It should be noted that similar regions of the structure 200 of FIG. 2A and the structure 100 of FIG. 1E have the same reference numerals, except for the first digit, which is used to indicate the figure number. For instance, an interconnect layer 230 (FIG. 2A) and the interconnect layer 130 (FIG. 1E) are similar.

Next, in one embodiment, the structure 200 is diced (by a laser beam (not shown) in one embodiment) at the dicing channel region 218 until a portion of the semiconductor substrate 210 is removed, resulting in a dicing trench 216 (FIG. 2B).

Next, with reference to FIG. 2C, in one embodiment, a dielectric layer 240 (comprising nitride in one embodiment) is formed on top of the entire structure 200 of FIG. 2B. The nitride layer 240 can be formed by CVD of silicon nitride on top of the entire structure 200 of FIG. 2B. It should be noted that the nitride layer 240 is on side walls and a bottom wall of the dicing trench 216.

Next, with reference to FIG. 2D, in a manner similar to what is described in FIGS. 1H-1N, pads 250 a, 250 b, and 250 c, a PSPI layer 260, a BLM region 270, a solder bump 271, a laminate substrate 280, and an underfill layer 290 are formed.

It should be noted that the coefficients of thermal extension (CTE) of the nitride layer 240 and the interconnect layers 220 and 230 are not large, and that these layers are thin. Therefore, splits are not likely to occur at a side wall 215 (the interfacing surface between the nitride layer 240 and the interconnect layers 220 and 230 in FIG. 2D).

In the embodiments above, the semiconductor chip has two interconnect layers. In general, it can have any number of interconnect layers (e.g., 10, 12, etc.).

While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention. 

1. A chip fabrication method, comprising: providing a structure which includes: (a) a semiconductor substrate; (b) a transistor on the semiconductor substrate, and (c) N interconnect layers on top of the semiconductor substrate and the transistor, wherein N is a positive integer greater than two, and wherein the transistor is electrically coupled to the N interconnect layers; forming a first dielectric layer on top of the N interconnect layers; forming a second dielectric layer on top of the first dielectric layer, wherein the second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers; forming a solder bump on the N interconnect layers, wherein the solder bump is electrically coupled to the transistor through the N interconnect layers; forming a laminate substrate on top of the solder bump; and forming an underfill layer being sandwiched between the second dielectric layer and the laminate substrate, wherein the second dielectric layer is sandwiched between the first dielectric layer and the underfill layer, and wherein the underfill layer is not in direct physical contact with any interconnect layer of the N interconnect layers.
 2. The method of claim 1, wherein the first dielectric layer comprises silicon nitride.
 3. The method of claim 2, wherein the second dielectric layer comprises polyimide.
 4. The method of claim 3, wherein the underfill layer comprises epoxy.
 5. The method of claim 1, further comprising: providing an edge seal region and a split stop region in the N interconnect layers, wherein the edge seal region forms a first closed loop on a perimeter of the semiconductor chip, and wherein the split stop region forms a second closed loop on a perimeter of the semiconductor chip.
 6. The method of claim 1, wherein the first dielectric layer extends in a first direction, and wherein the second dielectric layer comprises a first portion extending in the first direction and a second portion extending in a second direction perpendicular to the first direction.
 7. The method of claim 6, wherein the first portion is not in direct physical contact with each said interconnect layer of the N interconnect layers, and wherein the second portion is in direct physical contact with each said interconnect layer of the N interconnect layers.
 8. A chip fabrication method, comprising: providing a structure which includes: (a) a semiconductor substrate; (b) a transistor on the semiconductor substrate; and (c) N interconnect layers on top of the semiconductor substrate and the transistor, wherein N is a positive integer greater than two, and wherein the transistor is electrically coupled to the N interconnect layers; forming a first dielectric layer on top of the N interconnect layers, wherein a first planer vertical surface of the first dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers; forming a second dielectric layer on top of the first dielectric layer; forming an underfill layer on top of the second dielectric layer, wherein the second dielectric layer is sandwiched between the first dielectric layer and the underfill layer; and forming a laminate substrate on top of the underfill layer, wherein the underfill layer is sandwiched between the second dielectric layer and the laminate substrate.
 9. The method of claim 8, wherein the first dielectric layer comprises silicon nitride.
 10. The method of claim 9, wherein the second dielectric layer comprises polyimide.
 11. The method of claim 10, wherein the underfill layer comprises epoxy.
 12. The method of claim 8, wherein the underfill layer is not in direct physical contact with any interconnect layer of the N interconnect layers.
 13. The method of claim 8, further comprising: providing an edge seal region and a split stop region in the N interconnect layers, wherein the edge seal region forms a first closed loop on a perimeter of the semiconductor chip, and wherein the split stop region forms a second closed loop on a perimeter of the semiconductor chip.
 14. The method of claim 8, wherein the first dielectric layer comprises a first portion extending in a first direction and a second portion extending in a second direction perpendicular to the first direction, and wherein the second dielectric layer comprises a first portion extending in the first direction and a second portion extending the second direction.
 15. The method of claim 14, wherein the first portion of the first dielectric layer is not in direct physical contact with each said interconnect layer of the N interconnect layers, and wherein the second portion of the first dielectric layer is in direct physical contact with each said interconnect layer of the N interconnect layers.
 16. The method of claim 14, wherein the first dielectric layer comprises a third portion extending in the first direction, wherein the first portion of the first dielectric layer is parallel to the third portion of the first dielectric layer, and wherein the first portion of the first dielectric layer is not in a same plane as the third portion of the first dielectric layer.
 17. The method of claim 14, further comprising: forming a nitride layer between a first interconnect layer of the N interconnect layers and a second interconnect layer of the N interconnect layers, wherein said nitride layer is in direct physical contact with the first planer vertical surface of the first dielectric layer; and forming a boro-phospho-silicate glass layer between the first interconnect layer of the N interconnect layers and the semiconductor substrate, wherein the boro-phospho-silicate glass layer is in direct physical contact with the first planer vertical surface of the first dielectric layer.
 18. The method of claim 14, wherein said first planer vertical surface of the first dielectric layer is in direct physical contact with the semiconductor substrate, and wherein said first planer vertical surface of the first dielectric layer is in direct physical contact with a non-conductive portion of each said interconnect layer of the N interconnect layers. 